1. Field of the Invention
The present invention relates generally to CMOS imaging devices, and more particularly to an imaging system-on-chip implementation for producing high performance image sensors having high resolution, low power dissipation and noise.
2. Description of the Related Art
Visible imaging systems implemented in CMOS significantly reduce video camera cost and power by efficiently combining the image sensor with the ancillary components including drive electronics and output signal conditioning electronics. A video camera, for example, can be configured as a single CMOS integrated circuit supported by only an oscillator and a battery. Such a CMOS imaging system-on-chip requires lower voltages and dissipates less power than a CCD-based system with supporting camera system. These improvements translate into smaller camera size, longer battery life, and applicability to many new products.
The advantages offered by CMOS visible imagers have spurred considerable effort to develop active-pixel sensor (APS) devices. Active-pixel sensors with on-chip analog and/or digital signal processing can provide low temporal noise comparable or superior to scientific grade CCD systems. CMOS active-pixel circuits, on the other hand, can increase fixed pattern noise (possibly requiring additional camera circuitry to suppress the noise) and limit image sensor scalability to preclude producing sufficiently high resolution to produce digital images having quality comparable to photographic film.
Consequently, the CMOS image sensor design must optimize the entire architecture starting at the pixel through the on-chip digitizer to produce the highest quality video stream. Much prior art addresses only one or few aspects of the imaging system-on-chip to constrain the overall challenge. Prior art in the late 1960's to the late 1980's strove to optimize the total solution without having access to modern deep submicron CMOS processes by various means including 3-D assembly to incorporate on-focal plane A/D conversion, gain and offset compensation, and image sensor control. More recent prior art used amalgamated CCD/CMOS technology or inchoate CMOS technology to architect system-on-chip solutions.
For example, U.S. Pat. No. 6,456,326 suppresses pixel-based fixed pattern noise by applying conventional correlated double sampling to a relatively complex pixel design that offers low temporal noise, but does not achieve overall fixed-pattern noise below 0.2% (Col. 5, Line 23). Alternative image sensors that are competitive to incumbent CCDs must have fixed pattern noise at least an order of magnitude lower. Nevertheless, no means is taught to suppress the column-based noise produced by either the subsequent column-based signal conditioning or A/D conversion. Moreover, scalability and compatibility with foundry processes are not taught since floating gates transparent to visible wavelengths of interest are not generally available. The result in FIG. 2 is unsatisfactory quantum efficiency less than 10% in the blue region. Furthermore, the sampling node is vulnerable to signal discharge due to stray light and this parasitic effect degrades the quality of the captured image.
U.S. Pat. No. 5,471,515 also teaches an active pixel to facilitate lower temporal and spatial noise that is similarly incompatible with scaling and production at leading foundries using conventional CMOS image sensor processes. It is critical that the photogate be transparent to broadband radiation, yet supporting gate materials such as Indium Tin Oxide (ITO) are unavailable with mainstream CMOS technology. This incompatibility applies as well to U.S. Pat. No. 6,624,850 taught by Guidash, but the latter is more scalable by using only four transistors in each pixel.
U.S. Pat. No. 5,880,460 teaches means for suppressing pixel-based noise and the camera-on-chip noise specifically generated by sampling power supply noise on a row-by-row basis. Here the common mode signal is subtracted to reduce total read noise to the level set only by the pixel design, but no means is supplied to suppress the noise of the subsequent signal conditioning that is downstream of the pixel.
Fox in U.S. Pat. No. 6,566,697 teaches a pixel design potentially compatible with CMOS foundry production, but the method has limited scalability to smaller pixel pitch to produce multi-megapixel imager format since it comprises five transistors. Implementation of the pinned diode can also be problematic with conventional CMOS process technology since low voltage operation results in a charge transfer barrier between the diode and the sampling node 18 as shown in FIG. 3C that manifests image lag. Further, the high impedance node 18 both generates reset noise and is vulnerable to pickup of feed-through offsets that create fixed pattern noise.
In addition to optimum pixel design, a low-noise CMOS imaging system-on-chip requires support circuits to manage the photo-generated signal from each pixel. U.S. Pat. No. 5,471,515 shows one method for handling the signal and reset levels from each pixel to facilitate correlated double sampling. Guidash teaches pixel miniaturization in combination with the downstream circuit means of U.S. Pat. No. 5,471,515 by combining clocking functions to remove one transistor from each pixel. Unfortunately, these methodologies again work best when supported with transparent gate technology.
Further downstream, the CMOS imaging system-on-chip requires on-chip digitization. Mainstream methods include column-wise A/D conversion as taught by Chen (“PASIC: A processor-A/D converter sensor integrated circuit” in Circuits and Systems, 1990, IEEE International Symposium on, 1–3 May 19 pp 1705–1708 vol. 3) to produce a camera-on-chip implementation including timing controller; or Chen, (“PASIC. A sensor/processor array for computer vision,” Proceedings of the International Conference on Application Specific Array Processors, 5–7 Sep. 1990, pp. 352–366) to facilitate very high frame rates. By having a relatively low-speed A/D converter at each column, such as also taught by Gowda in U.S. Pat. No. 6,115,066, the total video frame rate can be very high. Mitigation of non-uniformities between the many digitizers, however, requires global calibration via means such as taught by Lee in U.S. Pat. No. 6,583,817. Another problem is the relative high power dissipation of this technology path since each ADC's power dissipation is high compared to higher speed digitizers. The quiescent operating point for low-speed through high-speed converters requires basic power dissipation levels that weakly depend on digitization frequency. Basic power efficiency hence degrades as the digitization is made less global, such as by migrating from one converter per sensor, to several converters per sensor, to one converter per column (Chen), and to one converter per pixel (for example, as taught by Mandl in U.S. Pat. No. 5,248,971 and Fowler (ISSCC Digest of Technical Papers, San Francisco, Calif., February 1994).
As disclosed in U.S. Pat. No. 6,493,030, herein incorporated by reference, a scalable high-performance low-noise amplifier system for a CMOS image sensor that can be produced in standard CMOS process technology may be formed as shown in FIG. 1. Each pixel 10 in a sensor array (not shown) comprises a photodetector 12, such as a photodiode, for example, connected to the gate of a dual-driver MOSFET 14, and one leg of a reset MOSFET 16. The other leg of MOSFET 16 is connected to a leg of MOSFET 14 and a leg of MOSFET 20. MOSFET 20 acts as a current source during global reset and as a switch during pixel readout. A row select MOSFET 18 has one leg connected to MOSFET 14 and the other leg connected to column bus 24. Column bus 24 connects all the pixels in a column of the photodetector array by way of the row select MOSFET 18 to a source supply 30. Row bus 22 connects all the pixel resets in a row to an access supply Vdd. Tapered reset supply 50 supplies an optimized active-pixel reset waveform, as disclosed in the U.S. Pat. No. 6,493,030 patent and illustrated in FIG. 2, to the gate of MOSFET 16.
Reset is initiated by filly enabling the row select MOSFETs 18 of the pixels in the selected row, thereby connecting a low-impedance voltage source (located in source supply 30) to one leg of MOSFET 14 for all the pixels in the row. An embodiment of the source supply 30 is shown in FIG. 6. Dual purpose MOSFET 20 is biased as a current source by waveform Vbias on gate 26 so that all the pixel amplifiers in the imager are configured as transimpedance amplifiers with capacitive feedback provided by MOSFET'S 14 Miller capacitance. MOSFET 14 thus acts as a transconductance, and reset MOSFET 16 acts as a resistance controlled by the tapered reset supply 50. The series resistance of MOSFET 16 is gradually increased by applying a decreasing ramp waveform to the gate of MOSFET 16 to give the feedback transconductance of MOSFET 14 the opportunity to null the reset noise (kTC).
As described, MOSFET 20 is configured as a P-FET (see FIGS. 5 and 6 of the U.S. Pat. No. 6,493,030 patent), whereas the other transistors are N-FETs. In such a configuration, the distributed feedback amplifier is a simple inverter, and provides the gain necessary to facilitate the tapered reset noise suppression mechanism to suppress the reset noise.
As disclosed in U.S. Pat. No. 5,892,540, herein incorporated by reference, a high-performance low-noise amplifier system is formed that minimizes column-based fixed pattern noise while competently handling the signal from each pixel on a column-by-column basis. The read out circuit for each column of pixels includes a high gain, wide bandwidth, CMOS differential amplifier, a reset switch and selectable feedback capacitors, selectable load capacitors, correlated double sampling and sample-and-hold circuits, an optional pipelining circuit, and an offset cancellation circuit connected to an output bus to suppress the input offset non-uniformity of the column amplifier.